The present invention relates to a display system using a multiport memory as a frame buffer, especially a display system having means for drawing display data into the frame buffer asynchronously with reading out display data from the frame buffer for display.
In a prior art display system using a single-port memory as a frame buffer, it has been necessary to serially read out display data from the frame buffer. (This read out operation is called a read access for display, hereinafter.) Therefore, in order to draw display data into the frame buffer by a CPU (central processing unit), DMAC (direct memory access controller), etc., during the display, a time sharing of a read access for display cycle and a draw access cycle has been used, or the draw access cycle is executed during horizontal and vertical blanking periods. Namely, the read access for display has priority to the draw access, which is allotted during specially determined time slots.
In contrast, dual-port memories have recently become available to users in this technical area. The dual-port memories can be randomly accessed in parallel, and further sequentially accessed. That is, the dual port memory has a serial access memory part which is able to operate asynchronously and independently to a random access memory part thereof. Generally, the read access for a display is sequentially executed. Therefore, if the display data is transferred to the serial access memory part at first and sequentially read out, the draw access to the random access memory part can be done except data transfer periods to the serial access memory part, so that it become possible to make the draw access speed to the random access memory part higher. The dual port memories in the prior art are described, for example, in U.S. Pat. Nos. 4,347,587 and 4,498,155, etc.
In the display system using the dual port memories as the frame buffer, as mentioned above, it is possible to access the random access memory part for drawing except the data transfer periods from the random access memory part to the serial access memory part. In these type of memories, the data transfer time is the same as or nearly equal to the draw access cycle time. As a result, in this system, the draw access becomes to have priority over the read access for display.
In general, the draw access is generated asynchronously to the read access for display. Therefore, it is natural that timings for drawing data into the memories are generated asynchronously to timings for displaying data. Because, the timings of the read access for display are parameters based on a display apparatus, and the timings of the draw access are based on a clock frequency of the CPU for drawing data into the frame buffer.
However, since, in the prior display system using the dual port memories, there is no consideration in the asynchronousness, it is impossible to execute the read access for display cycle and the draw access cycle asynchronously. Therefore, there remain some problems in a case that the draw access arises near the timing of the read access for display.
FIG. 1 illustrates the timings in which the data transfer B occurs at the timing .beta. during the draw access A. In this case, the draw access A is executed normally, but the data transfer B can not be started at the timing .beta., so that noise of display screen is generated. Since in the dual port memory the display data is serially read out from the serial access memory part during the read access for display, the noise of display screen remains until the next data transfer is executed normally. Namely, in the prior display system using the dual port memories, there remains some possibility that the data transfer of the read access for display can not be executed perfectly.